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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7597 8-bit shift register with input latches Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-bit shift register with input latches FEATURES * 8-bit parallel input latches * Shift register has direct overriding load and clear * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT7597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT7597 The 74HC/HCT7597 both consist of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. When LE is LOW, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is HIGH the latches store the information that was present at the D-inputs, a set-up time preceding the LOW-to-HIGH transition of LE. The shift register has a positive edge-triggered clock, direct load (from storage) and clear inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay SHCP to Q LE to Q PL to Q D7 to Q fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF; VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". maximum clock frequency SHCP input capacitance power dissipation capacitance per package notes 1, 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 15 22 20 20 99 3.5 29 17 27 23 24 79 3.5 30 ns ns ns ns MHz pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification 8-bit shift register with input latches PIN DESCRIPTION PIN NO. 8 9 10 11 12 13 14 15, 1, 2, 3, 4, 5, 6, 7 16 SYMBOL GND Q MR SHCP LE PL DS D0 to D7 VCC NAME AND FUNCTION ground (0 V) serial data output 74HC/HCT7597 asynchronous reset input (active LOW) shift clock input (LOW-to-HIGH, edge-triggered) latch enable input (active LOW) parallel load input (active LOW) serial data input parallel data inputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 8-bit shift register with input latches FUNCTION TABLE LE L H X X X X Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH CP transition SHCP X X X X X PL X X L L H H MR X X H L L H FUNCTION data enabled to input latches (transparent) data stored into latches (non-transparent) data transferred from input latches to shift register 74HC/HCT7597 invalid logic, state of shift register indeterminate when signals removed shift register cleared shift register clocked Qn = Qn-1, Q0 = DS Fig.4 Functional diagram. December 1990 4 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 Fig.5 Logic diagram. December 1990 5 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 Fig.6 Timing diagram. December 1990 6 Philips Semiconductors Product specification 8-bit shift register with input latches DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. max. 265 53 45 265 53 45 375 75 64 285 57 48 285 57 48 110 22 19 120 24 20 120 24 20 120 24 20 120 24 20 75 15 13 ns 74HC/HCT7597 TEST CONDITIONS UNIT V CC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 min. typ. max. min. max. tPHL/ tPLH propagation delay SHCP to Q propagation delay MR to Q propagation delay LE to Q propagation delay PL to Q propagation delay D7 to Q output transition time 50 18 14 52 19 15 72 26 21 63 23 18 63 23 18 19 7 6 80 16 14 80 16 14 80 16 14 80 16 14 50 10 9 11 4 3 11 4 3 17 6 5 17 6 5 -3 -1 -1 175 35 30 175 35 30 250 50 43 190 38 32 190 38 32 75 15 13 100 20 17 100 20 17 100 20 17 100 20 17 65 13 11 220 44 37 220 44 37 315 63 54 240 48 41 240 48 41 95 19 16 tPHL ns Fig.7 tPHL/ tPLH ns Fig.7 tPHL/ tPLH ns Fig.7 tPHL/ tPLH ns Fig.7 tTHL/ tTLH ns Fig.7 tW SHCP pulse width HIGH or LOW LE pulse width LOW MR pulse width LOW PL pulse width LOW removal time MR to SHCP ns Fig.7 tW ns Fig.7 tW ns Fig.7 tW ns Fig.7 trem ns Fig.7 December 1990 7 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. 150 30 26 120 24 20 120 24 20 120 24 20 4 4 4 2 2 2 2 2 2 4.0 20 24 max. ns TEST CONDITIONS UNIT V CC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 min. typ. max. min. max. trem removal time MR to PL set-up time Dn to LE set-up time DS to SHCP set-up time PL to SHCP hold time Dn to LE hold time DS to SHCP hold time PL to SHCP 100 20 17 80 16 14 80 16 14 80 16 14 4 4 4 2 2 2 2 2 2 22 8 6 6 2 2 11 4 3 8 3 2 -3 -1 -1 -8 -3 -2 -8 -3 -2 30 90 107 125 25 21 100 20 17 100 20 17 100 20 17 4 4 4 2 2 2 2 2 2 4.8 24 28 tsu ns Fig.7 tsu ns Fig.7 tsu ns Fig.7 th ns Fig.7 th ns Fig.7 th ns Fig.7 fmax maximum pulse frequency 6.0 SHCP 30 35 MHz Fig.7 December 1990 8 Philips Semiconductors Product specification 8-bit shift register with input latches DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI 74HC/HCT7597 Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT DS Dn PL, MR LE, SHCP UNIT LOAD COEFFICIENT 0.25 0.40 1.50 1.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. 53 63 80 69 74 22 24 24 30 27 15 30 ns ns ns ns ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 UNIT VCC WAVEFORMS (V) TEST CONDITIONS min. typ. max. min. max. min. tPHL/ tPLH tPHL tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW tW tW tW trem trem propagation delay SHCP to Q propagation delay MR to Q propagation delay LE to Q propagation delay PL to Q propagation delay D7 to Q output transition time SHCP pulse width HIGH or LOW LE pulse width LOW MR pulse width LOW PL pulse width LOW removal time MR to SHCP removal time MR to PL 16 16 20 18 10 20 20 25 31 27 28 7 6 7 11 9 -1 9 35 42 53 46 49 15 20 20 25 23 13 25 44 53 66 58 61 19 December 1990 9 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. ns ns ns ns ns ns MHz UNIT TEST CONDITIONS VCC WAVEFORMS (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 min. typ. max. min. max. min. tsu tsu tsu th th th fmax set-up time Dn to LE set-up time DS to SHCP set-up time PL to SHCP hold time Dn to LE hold time DS to SHCP hold time PL to SHCP 16 16 16 4 2 2 5 5 3 -2 -4 -3 72 20 20 20 4 2 2 24 24 24 24 4 2 2 20 maximum pulse frequency 30 SHCP December 1990 10 Philips Semiconductors Product specification 8-bit shift register with input latches AC WAVEFORMS 74HC/HCT7597 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the SHCP input to Q output propagation delays, the SHCP pulse width and maximum clock pulse frequency. Fig.8 Waveforms showing the MR input to Q output propagation delay and the MR pulse width. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the LE input to Q output propagation delays and the LE pulse width. Fig.10 Waveforms showing the PL input to Q output propagation delays, PL pulse width and output transition times. December 1990 11 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the D7 input to Q output propagation delays and output transition times. Fig.12 Waveforms showing the MR input to PL, SHCP removal times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.14 Waveforms showing set-up and hold times for PL input to SHCP input. Fig.13 Waveforms showing hold and set-up times for DS, Dn inputs to SHCP, LE inputs. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 12 |
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